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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a single supply, rail-to-rail low power, fet-input op amp features single supply operation: 3 v to 30 v very low input bias current: 2 pa wide input voltage range rail-to-rail output swing low supply current: 500 m a/amp wide bandwidth: 2 mhz slew rate: 2 v/ m s no phase reversal applications photo diode preamplifier battery powered instrumentation power supply control and protection medical instrumentation remote sensors low voltage strain gage amplifiers dac output amplifier general description the ad824 is a quad, fet input, single supply amplifier, fea- turing rail-to-rail outputs. the combination of fet inputs and rail-to-rail outputs makes the ad824 useful in a wide variety of low voltage applications where low input current is a primary consideration. the ad824 is guaranteed to operate from a 3 v single supply up to 15 volt dual supplies. fabricated on adis complementary bipolar process, the ad824 has a unique input stage that allows the input voltage to safely extend beyond the negative supply and to the positive supply without any phase inversion or latchup. the output voltage swings to within 15 millivolts of the supplies. capacitive loads to 350 pf can be handled without oscillation. the fet input combined with laser trimming provides an input that has extremely low bias currents with guaranteed offsets be- low 300 m v. this enables high accuracy designs even with high source impedances. precision is combined with low noise, making the ad824 ideal for use in battery powered medical equipment. pin configurations 14-lead epoxy dip (n suffix) 14-lead epoxy so (r suffix) out a ?n a out d ?n d +inb ?nb outb +in c ?n c out c +in a v+ +in d v 1 2 14 13 5 6 7 10 9 8 3 4 12 11 top view (not to scale) ad824 out a ?n a out d ?n d +in b ?n b out b +in c ?n c out c +in a v+ +in d v 1 2 14 13 5 6 7 10 9 8 3 4 12 11 top view ad824 ad824 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 16-lead epoxy so (r suffix) 1 2 3 4 5 6 7 8 14 13 12 11 10 9 15 16 out a ?n a +in a v+ +in b ?n b out b ?n d +in d v +in c ?n c out c out d nc nc nc = no connect ad824 applications for the ad824 include portable medical equipment, photo diode preamplifiers and high imped ance transducer amplifiers. the ability of the output to swing rail-to-rail enables designers to build multistage filters in single supply systems and maintain high signal-to-noise ratios. the ad824 is specified over the extended industrial (C40 c to +85 c) temperature range and is available in 14-pin dip and narrow 14-pin and 16-pin so packages.
ad824Cspecifications electrical specifications parameter symbol conditions min typ max units input characteristics offset voltage ad824a v os 0.1 1.0 mv t min to t max 1.5 mv offset voltage ad824b v os 300 m v t min to t max 900 m v input bias current i b 212pa t min to t max 300 4000 pa input offset current i os 210pa t min to t max 300 pa input voltage range C0.2 3.0 v common-mode rejection ratio cmrr v cm = 0 v to 2 v 66 80 db v cm = 0 v to 3 v 60 74 db t min to t max 60 db input impedance 10 13 i 3.3 w i pf large signal voltage gain a vo v o = 0.2 v to 4.0 v r l = 2 k w 20 40 v/mv r l = 10 k w 50 100 v/mv r l = 100 k w 250 1000 v/mv t min to t max, r l = 100 k w 180 400 v/mv offset voltage drift d v os / d t2 m v/ c output characteristics output voltage high v oh i source = 20 m a 4.975 4.988 v t min to t max 4.97 4.985 v i source = 2.5 ma 4.80 4.85 v t min to t max 4.75 4.82 v output voltage low v ol i sink = 20 m a1525mv t min to t max 20 30 mv i sink = 2.5 ma 120 150 mv t min to t max 140 200 mv short circuit limit i sc sink/source 12 ma t min to t max 10 ma open-loop impedance z out f = 1 mhz, a v = 1 100 w power supply power supply rejection ratio psrr v s = 2.7 v to 12 v 70 80 db t min to t max 66 db supply current/amplifier i sy t min to t max 500 600 m a dynamic performance slew rate sr r l = 10 k w , a v = 1 2 v/ m s full-power bandwidth bw p 1% distortion, v o = 4 v p-p 150 khz settling time t s v out = 0.2 v to 4.5 v, to 0.01% 2.5 m s gain bandwidth product gbp 2 mhz phase margin f o no load 50 degrees channel separation cs f = 1 khz, r l = 2 k w C123 db noise performance voltage noise e n p-p 0.1 hz to 10 hz 2 m v p-p voltage noise density e n f = 1 khz 16 nv/ ? hz current noise density i n f = 1 khz 0.8 fa/ ? hz total harmonic distortion thd f = 10 khz, r l = 0, a v = +1 0.005 % (@ v s = +5.0 v, v cm = 0 v, v out = 0.2 v, t a = +25 8 c unless otherwise noted) C2C rev. a
electrical specifications parameter symbol conditions min typ max units input characteristics offset voltage ad824a v os 0.5 2.5 mv t min to t max 0.6 4.0 mv offset voltage ad824b v os 0.5 1.5 mv t min to t max 0.6 2.5 mv input bias current i b v cm = 0 v 4 35 pa t min to t max 500 4000 pa input bias current i b v cm = C10 v 25 pa input offset current i os 320 pa t min to t max 500 pa input voltage range C15 13 v common-mode rejection ratio cmrr v cm = C15 v to 13 v 70 80 db t min to t max 66 db input impedance 10 13 i 3.3 w i pf large signal voltage gain a vo vo = C10 v to +10 v; r l = 2 k w 12 50 v/mv r l = 10 k w 50 200 v/mv r l = 100 k w 300 2000 v/mv t min to t max, r l = 100 k w 200 1000 v/mv offset voltage drift d v os / d t2 m v/ c output characteristics output voltage high v oh i source = 20 m a 14.975 14.988 v t min to t max 14.970 14.985 v i source = 2.5 ma 14.80 14.85 v t min to t max 14.75 14.82 v output voltage low v ol i sink = 20 m a C14.985 C14.975 v t min to t max C14.98 C14.97 v i sink = 2.5 ma C14.88 C14.85 v t min to t max C14.86 C14.8 v short circuit limit i sc sink/source, t min to t max 8 20 ma open-loop impedance z out f = 1 mhz, a v = 1 100 w power supply power supply rejection ratio psrr v s = 2.7 v to 15 v 70 80 db t min to t max 68 db supply current/amplifier i sy v o = 0 v 560 625 m a t min to t max 675 m a dynamic performance slew rate sr r l = 10 k w , a v = 1 2 v/ m s full-power bandwidth bw p 1% distortion, v o = 20 v p-p 33 khz settling time t s v out = 0 v to 10 v, to 0.01% 6 m s gain bandwidth product gbp 2 mhz phase margin f o 50 degrees channel separation cs f = 1 khz, r l =2 k w C123 db noise performance voltage noise e n p-p 0.1 hz to 10 hz 2 m v p-p voltage noise density e n f = 1 khz 16 nv/ ? hz current noise density i n f = 1 khz 1.1 fa/ ? hz total harmonic distortion thd f =10 khz, v o = 3 v rms, r l = 10 k w 0.005 % (@ v s = 6 15.0 v, v out = 0 v, t a = +25 8 c unless otherwise noted) ad824 C3C rev. a
ad824Cspecifications electrical specifications parameter symbol conditions min typ max units input characteristics offset voltage ad824a -3 v v os 0.2 1.0 mv t min to t max 1.5 mv input bias current i b 212pa t min to t max 250 4000 pa input offset current i os 210pa t min to t max 250 pa input voltage range 0 1 v common-mode rejection ratio cmrr v cm = 0 v to 1 v 58 74 db t min to t max 56 db input impedance 10 13 i 3.3 w i pf large signal voltage gain a vo v o = 0.2 v to 2.0 v r l = 2 k w 10 20 v/mv r l = 10 k w 30 65 v/mv r l = 100 k w 180 500 v/mv t min to t max, r l = 100 k w 90 250 v/mv offset voltage drift d v os / d t2 m v/ c output characteristics output voltage high v oh i source = 20 m a 2.975 2.988 v t min to t max 2.97 2.985 v i source = 2.5 ma 2.8 2.85 v t min to t max 2.75 2.82 v output voltage low v ol i sink = 20 m a1525mv t min to t max 20 30 mv i sink = 2.5 ma 120 150 mv t min to t max 140 200 mv short circuit limit i sc sink/source 8ma short circuit limit i sc sink/source, t min to t max 6ma open-loop impedance z out f = 1 mhz, a v = 1 100 w power supply power supply rejection ratio psrr v s = 2.7 v to 12 v, 70 db t min to t max 66 db supply current/amplifier i sy v o = 0.2 v, t min to t max 500 600 m a dynamic performance slew rate sr r l =10 k w , a v = 1 2 v/ m s full-power bandwidth bw p 1% distortion, v o = 2 v p-p 300 khz settling time t s v out = 0.2 v to 2.5 v, to 0.01% 2 m s gain bandwidth product gbp 2 mhz phase margin f o 50 degrees channel separation cs f = 1 khz, r l = 2 k w C123 db noise performance voltage noise e n p-p 0.1 hz to 10 hz 2 m v p-p voltage noise density e n f = 1 khz 16 nv/ ? hz current noise density i n 0.8 fa/ ? hz total harmonic distortion thd f = 10 khz, r l = 0, a v = +1 0.01 % (@ v s = +3.0 v, v cm = 0 v, v out = 0.2 v, t a = +25 8 c unless otherwise noted) C4C rev. a
ad824 rev. a C5C wafer test limits parameter symbol conditions limit units offset voltage v os 1.0 mv max input bias current i b 12 pa max input offset current i os 20 pa input voltage range v cm C0.2 to 3.0 v min common-mode rejection ratio cmrr v cm = 0 v to 2 v 66 db min power supply rejection ratio psrr v = + 2.7 v to +12 v 70 m v/v large signal voltage gain a vo r l = 2 k w 15 v/mv min output voltage high v oh i source = 20 m a 4.975 v min output voltage low v ol i sink = 20 m a 25 mv max supply current/amplifier i sy v o = 0 v, r l = 600 m a max note electrical tests and wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. (@ v s = +5.0 v, v cm = 0 v, t a = +25 8 c unless otherwise noted) warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad824 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage . . . . . . . . . . . . . . . . . . . . . . . Cv s C 0.2 v to +v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 30 v output short circuit duration to gnd . . . . . . . . . indefinite storage temperature range n, r package . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range ad824a, b . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature range n, r package . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c package type q ja 2 q jc units 14-pin plastic dip (n) 76 33 c/w 14-pin soic (r) 120 36 c/w 16-pin soic (r) 92 27 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts unless otherwise noted. 2 q ja is specified for the worst case conditions, i.e., q ja is specified for device in socket for p-dip packages; q ja is specified for device soldered in circuit board for soic package. ordering guide temperature model range package option ad824an C40 c to +85 c 14-pin plastic dip ad824bn C40 c to +85 c 14-pin plastic dip AD824AR C40 c to +85 c 14-pin soic AD824AR-3v C40 c to +85 c 14-pin soic ad824an-3v C40 c to +85 c 14-pin plastic dip AD824AR-14 C40 c to +85 c 14-pin soic AD824AR-14-3v C40 c to +85 c 14-pin soic AD824AR-16 C40 c to +85 c 16-pin soic ad824achips +25 c dice dice characteristics ad824 die size 0.70 x 0.130 inch, 9,100 sq. mils. substrate (die backside) is connected to v+. transistor count, 143. i6 r1 r2 r9 r7 r17 r14 r12 r13 r15 v cc i5 q18 q29 q27 q21 q20 q23 q25 q24 q31 q28 q22 q19 q7 q6 q5 q8 q3 q2 q4 i1 i2 i3 i4 +in j1 ?n c1 q26 v out j2 v ee c3 c2 c4 figure 1. simplified schematic of 1/4 ad824
ad824Ctypical characteristics 100 10m 1k 10k 100k 1m 80 60 40 20 0 gain ?db 180 135 90 45 phase ?degrees v s = +5v no load 10 0% 100 90 1? 50mv figure 4. open-loop gain/phase and small signal response, v s = +5 v, no load 10m 1k 10k 100k 1m 60 40 20 0 ?0 gain ?db 180 135 90 45 phase ?degrees v s = +5v c l = 220pf 10 0% 100 90 1? 50mv figure 5. open-loop gain/phase and small signal response, v s = +5 v, c l = 220 pf 100 10m 1k 10k 100k 1m v s = 15v no load 80 60 40 20 0 gain ?db 180 135 90 45 phase ?degrees 10 0% 100 90 1? 50mv figure 2. open-loop gain/phase and small signal response, v s = 15 v, no load v s = 15v c l = 100pf 100 10m 1k 10k 100k 1m 80 60 40 20 0 gain ?db 180 135 90 45 phase ?degrees 10 0% 100 90 1? 50mv figure 3. open-loop gain/phase and small signal response, v s = 15 v, c l = 100 pf C6C rev. a
ad824 10m 1k 10k 100k 1m 60 40 20 0 ?0 gain ?db 180 135 90 45 phase ?degrees v s = +3v no load 10 0% 100 90 1? 50mv figure 6. open-loop gain/phase and small signal response, v s = +3 v, no load 10m 1k 10k 100k 1m 60 40 20 0 ?0 gain ?db 180 135 90 45 phase ?degrees v s = +3v c l = 220pf 10 0% 100 90 1? 50mv figure 7. open-loop gain/phase and small signal response, v s = +3 v, c l = 220 pf 10 0% 100 90 2? 5v 10.810 ? t figure 8. slew rate, r l = 10k 10 0% 100 90 2? 5v 9.950 ? t 10 0% 100 90 100? 5v v out figure 9. phase reversal with inputs exceeding supply by 1 volt load current ?a 0.8 0 1 10m 5 10 50 100 500 1m 5m 0.7 0.4 0.3 0.2 0.1 0.6 0.5 source sink output to rail ?volts figure 10. output voltage to supply rail vs. sink and source load currents rev. a C7C
ad824Ctypical characteristics offset voltage drift number of units 14 0 ?.5 2.5 ?.0 ?.5 ?.0 ?.5 0 0.5 1.0 1.5 2.0 12 10 8 6 4 2 count = 60 figure 14. tc v os distribution, C55 c to +125 c, v s = 5, 0 temperature ? c 150 ?5 ?0 140 ?0 ?0 0 20 40 60 80 100 120 125 100 75 50 25 0 input offset current ?pa v s = 5, 0 figure 15. input offset current vs. temperature input bias current ?pa temperature ? c 100k 20 140 40 60 80 100 120 10k 1k 100 10 1 v s = 5, 0 figure 16. input bias current vs. temperature +3v v s 15v 5 10 15 20 frequency ?khz 60 40 20 noise density ?nv/ ? hz figure 11. voltage noise density 0.1 0.010 0.001 0.0001 20 100 1k 10k 20k r l = 0 a v = +1 v s = +3 v s = +5 v s = 15 frequency ?hz thd+n ?% figure 12. total harmonic distortion offset voltage ?mv number of units 280 0 ?.5 0.5 ?.4 ?.3 ?.2 ?.1 0 0.1 0.2 0.3 0.4 240 200 160 120 80 40 count = 860 figure 13. input offset distribution, v s = 5, 0 rev. a C8C
ad824 rev. a C9C frequency ?hz 120 0 10 10m 100 1k 10k 100k 1m 100 80 60 40 20 common-mode rejection ?db figure 17. common-mode rejection vs. frequency thd ?db frequency ?hz ?0 ?0 ?20 100 100k 1k 10k ?0 ?00 figure 18. thd vs. frequency, 3 v rms frequency ?hz 100 ?0 10 10m 100 open-loop gain ?db 1k 10k 100k 1m 80 60 40 20 0 100 ?0 80 60 40 20 0 phase margin ?degrees 15v +3, 0v figure 19. open-loop gain and phase vs. frequency . . . frequency ?hz 1k input voltage noise ?nv/ ? hz 100 1 1 100k 10 100 1k 10k 10 figure 20. input voltage noise spectral density vs. frequency frequency ?hz 120 0 10 10m 100 power supply rejection ?db 1k 10k 100k 1m 100 80 60 40 20 figure 21. power supply rejection vs. frequency input frequency ?hz 30 0 1k 1m 3k output voltage ?volts 10k 30k 100k 300k 25 20 15 10 5 figure 22. large signal frequency response
ad824 C10C rev. a frequency ?hz ?0 ?40 10 100 crosstalk ?db 1k 10k 100k ?0 ?00 ?10 ?20 ?30 1 to 4 1 to 2 1 to 3 figure 23. crosstalk vs. frequency frequency ?hz 10k .01 10 10m 100 output impedance ? w 1k 10k 100k 1m 1k 100 10 1 .1 figure 24. output impedance vs. frequency, gain = +1 figure 25. small signal response, unity gain follower, 10k i 100 pf load 10 0% 100 90 500ns 20mv figure 26. large signal response temperature ? c 2750 1000 ?0 140 ?0 supply current ?? ?0 0 20 40 60 80 100 120 2500 2250 2000 1750 1500 1250 v s = 15v v s = 3, 0 figure 27. supply current vs. temperature output saturation voltage ?mv load current ?ma 1000 100 0 0.01 10.0 0.10 1.0 10 v ol ?v s v s ?v oh v s = 15v v s = 3, 0 figure 28. output saturation voltage 10 0% 100 90 5? 5v
ad824 rev. a C11C a current-limiting resistor should be used in series with the in- put of the ad824 if there is a possibility of the input voltage ex- ceeding the positive supply by more than 300 mv or if an input voltage will be applied to the ad824 when v s = 0. the ampli- fier will be damaged if left in that condition for more than 10 seconds. a 1 k w resistor allows the amplifier to withstand up to 10 volts of continuous overvoltage and increases the input volt- age noise by a negligible amount. input voltages less than Cv s are a completely different story. the amplifier can safely withstand input voltages 20 volts below the minus supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 volts. in ad- dition, the input stage typically maintains picoamp level input currents across that input voltage range. output characteristics the ad824s unique bipolar rail-to-rail output stage swings within 15 mv of the positive and negative supply voltages. the ad824s approximate output saturation resistance is 100 w for both sourcing and sinking. this can be used to estimate output saturation voltage when driving heavier current loads. for instance, the saturation voltage will be 0.5 volts from either supply with a 5 ma current load. for load resistances over 20 k w , the ad824s input error voltage is virtually unchanged until the output voltage is driven to 180 mv of either supply. if the ad824s output is overdriven so as to saturate either of the output devices, the amplifier will recover within 2 m s of its input returning to the amplifiers linear operating region. direct capacitive loads will interact with the amplifiers effective output impedance to form an additional pole in the amplifiers feedback loop, which can cause excessive peaking on the pulse response or loss of stability. worst case is when the amplifier is used as a unity gain follower. figures 5 and 7 show the ad824s pulse response as a unity gain follower driving 220 pf. configu- rations with less loop gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects. noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. figure 30 shows a method for extending capacitance load drive capability for a unity gain follower. with these component val- ues, the circuit will drive 5,000 pf with a 10% overshoot. 8 4 0.01 m f 20pf 20k w 100 w v out +v s ? s 0.01 m f c l 1/4 ad824 v i n figure 30. extending unity gain follower capacitive load capability beyond 350 pf application notes input characteristics in the ad824, n-channel jfets are used to provide a low offset, low noise, high impedance input stage. minimum input common-mode voltage extends from 0.2 v below Cv s to 1 v less than +v s . driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth. the ad824 does not exhibit phase reversal for input voltages up to and including +v s . figure 29a shows the response of an ad824 voltage follower to a 0 v to +5 v (+v s ) square wave in- put. the input and output are superimposed. the output tracks the input up to +v s without phase reversal. the reduced band- width above a 4 v input causes the rounding of the output wave form. for i nput voltages greater than +v s , a resistor in series with the ad824s noninverting input will prevent phase reversal at the expense of greater input voltage noise. this is illustrated in figure 29b. 10 0% 100 90 1v 1v 10? 1v 10 0% 100 90 1v 2? 1v gnd gnd +v s +5v r p v out v in figure 29. (a) response with r p = 0; v in from 0 to +v s (b) v in = 0 to + v s + 200 m v v out = 0 to + v s r p = 49.9 k w since the input stage uses n-channel jfets, input current dur- ing normal operation is positive; the current flows out from the input terminals. if the input voltage is driven more positive than +v s C 0.4 v, the input current will reverse direction as internal device junctions become forward biased. this is illustrated in figure 9. (b) (a)
ad824 C12C rev. a applications single supply voltage-to-frequency converter the circuit shown in figure 31 uses the ad824 to drive a low power timer, which produces a stable pulse of width t 1 . the positive going output pulse is integrated by r1-c1 and used as one input to the ad824, which is connected as a differential integrator. the other input (nonloading) is the unknown volt- age, v in . the ad824 output drives the timer trigger input, clos- ing the overall feedback loop. 2 6 5 3 4 +10v 0.1 m f c5 r scale ** 10k r1 499k, 1% r2 499k, 1% 0v to 2.5v full scale c1 0.01 m f, 2% c2 0.01 m f, 2% u4 ref02 u1 43 u3b 21 u3a c6 390pf 5% c3 0.1 m f thr tr dis rv+ out cv gnd 48 6 2 7 1 3 5 (npo) c4 0.01 m f r3 * 116k u2 cmos 555 out2 out1 notes: f out = /(vref*t 1 ), t 1 = 1.1*r3*c6 * = 1% metal film, <50ppm/ c tc ** = 10%, 20t film, <100ppm/ c tc t 1 = 33 m s for f out = 20khz @ = 2.0v = 25khz f s as shown. v ref = 5v cmos 74hco4 1/4 ad824b v in v in v in figure 31. single supply voltage-to-frequency converter typical ad824 bias currents of 2 pa allow megaohm-range source impedances with negligible dc errors. linearity errors on the order of 0.01% full scale can be achieved with this circuit. this performance is obtained with a 5 volt single supply, which delivers less than 3 ma to the entire circuit. single supply programmable gain instrumentation amplifier the ad824 can be configured as a single supply instrumenta- tion amplifier that is able to operate from single supplies down to 3 v or dual supplies up to 15 v. ad824 fet inputs 2 pa bias currents minimize offset errors caused by high unbalanced source impedances. an array of precision thin-film resistors sets the in amp gain to be either 10 or 100. these resistors are laser-trimmed to ratio match to 0.01% and have a maximum differential tc of 5 ppm/ c. table i. ad824 in amp performance parameters v s = 3 v, 0 v v s = 6 5 v cmrr 74 db 80 db common-mode voltage range C0.2 v to +2 v C5.2 v to +4 v 3 db bw, g = 10 180 khz 180 khz g = 100 18 khz 18 khz t settling 2 v step (v s = 0 v, 3 v) 2 m s 5 v (v s = 5 v) 5 m s noise @ f = 1 khz, g = 10 270 nv/ ? hz 270 nv/ ? hz g = 100 2.2 m v/ ? hz 2.2 m v/ ? hz 10 0% 100 90 1v 5? figure 32a. pulse response of in amp to a 500 mv p-p input signal; v s = +5 v, 0 v; gain = 10 (g =10) v out = (v in1 ?v in2 ) (1+ ) +v ref r6 r4 + r5 (g =100) v out = (v in1 ?v in2 ) (1+ ) +v ref for r1 = r6, r2 = r5 and r3 = r4 r5 + r6 r4 r1 r2 r3 r4 r5 r6 90k 9k 1k 1k 9k 90k v out v in1 0.1 m f 8 1/4 ad824 1/4 ad824 v in2 r p 1k w 1 2 3 6 5 11 7 ohmtek part # 1043 v ref g =10 g =100 r p 1k w g =100 g =10 +v s figure 32b. a single supply programmable instrumentation amplifier
ad824 rev. a C13C 3 volt, single supply stereo headphone driver the ad824 exhibits good current drive and thd+n perfor- mance, even at 3 v single supplies. at 1 khz, total harmonic distortion plus noise (thd+n) equals C62 db (0.079%) for a 300 mv p-p output signal. this is comparable to other single supply op amps that consume more power and cannot run on 3 v power supplies. in figure 33, each channels input signal is coupled via a 1 m f mylar capacitor. resistor dividers set the dc voltage at the noninverting inputs so that the output voltage is midway be- tween the power supplies (+1.5 v). the gain is 1.5. each half of the ad824 can then be used to drive a headphone channel. a 5 hz high-pass filter is realized by the 500 m f capacitors and the headphones, which can be modeled as 32 ohm load resistors to ground. this ensures that all signals in the audio frequency range (20 hzC20 khz) are delivered to the headphones. mylar 1? 1/4 ad824 l r headphones 32 w impedance 4.99k mylar 1? 4.99k 1/4 ad824 10k 10k 47.5k 95.3k 47.5k 500? 500? +3v 0.1? 0.1? channel 1 channel 2 95.3k figure 33. 3 volt single supply stereo headphone driver low dropout bipolar bridge driver the ad824 can be used for driving a 350 ohm wheatstone bridge. figure 34 shows one half of the ad824 being used to buffer the ad589a 1.235 v low power reference. the output 350 w 350 w 350 w 350 w v ref ? s +v s ad620 r g r2 20 w ?.5v 10k 10k 10k 26.4k, 1% r1 20 w to a/d converter reference input ad589 49.9k +1.235v +5v 1? gnd 1% 1% 1% 1/4 ad824 1/4 ad824 ? s +v s +v s ? s 0.1? ?v 1? 0.1? 7 6 5 4 3 2 figure 34. low dropout bipolar bridge driver of +4.5 v can be used to drive an a/d converter front end. the other half of the ad824 is configured as a unity-gain inverter and generates the other bridge input of C4.5 v. resistors r1 and r2 provide a constant current for bridge excitation. the ad620 low power instrumentation amplifier is used to condition the differential output voltage of the bridge. the gain of the ad620 is programmed using an external resistor r g and determined by: g = 49.4 k w r g + 1 a 3.3 volt/5 volt precision sample-and-hold amplifier in battery-powered applications, low supply voltage operational amplifiers are required for low power consumption. also, low supply voltage applications limit the signal range in precision analog circuitry. circ uits like the sample-and-hold circuit shown in figure 35, illustrate techniques for designing precision analog circuitry in low supply voltage applications. to maintain high signal-to-noise ratios (snrs) in a low supply voltage appli- cation requires the use of rail-to-rail, input/output operational amplifiers. this design highlights the ability of the ad824 to oper- ate rail-to-rail from a single +3 v/+5 v supply, with the advantages of high input impedance. the ad824, a quad jfet-input op amp, is well suited to s/h circuits due to its low input bias cur- rents (3 pa, typical) and high input impedances (3 10 13 w , typical). the ad824 also exhibits very low supply currents so the total supply current in this circuit is less than 2.5 ma. 3.3/5v 3.3/5v r1 50k r2 50k a1 3 2 4 1 11 0.1? false ground (fg) a4 12 13 14 sample/ hold a3 10 9 8 a2 5 6 7 15 14 16 10 9 11 ad824b 3.3/5v adg513 r5 2k w ad824c + v out c h c 500pf fg 4 5 8 6 7 23 1 ad824a ad824d r4 2k w fg 13 500pf fg figure 35. 3.3 v/5.5 v precision sample and hold in many single supply applications, the use of a false ground generator is required. in this circuit, r1 and r2 divide the sup- ply voltage symmetrically, creating the false ground voltage at one-half the supply. amplifier a1 then buffers this voltage cre- ating a low impedance output drive. the s/h circuit is config- ured in an inverting topology centered around this false ground level.
ad824 C14C rev. a a design consideration in sample-and-hold circuits is voltage droop at the output caused by op amp bias and switch leakage currents. by choosing a jfet op amp and a low leakage cmos switch, this design minimizes droop rate error to better than 0.1 m v/ m s in this circuit. higher values of c h will yield a lower droop rate. for best performance, c h and c2 should be poly- styrene, polypropylene or teflon capacitors. these types of capacitors exhibit low leakage and low dielectric absorption. addi- tionally, 1% metal film resistors were used throughout the design. in the sample mode, sw1 and sw4 are closed, and the output is v out = Cv in . the purpose of sw4, which operates in paral- lel with sw1, is to reduce the pedestal, or hold step, error by injecting the same amount of charge into the noninverting input of a3 that sw1 injects into the inverting input of a3. this cre- ates a common-mode voltage across the inputs of a3 and is then rejected by the cmr of a3; otherwise, the charge injection from sw1 would create a differential voltage step error that would appear at v out . the pedestal error for this circuit is less than 2 mv over the entire 0 v to 3.3 v/5 v signal range. another method of reducing pedestal error is to reduce the pulse ampli- tude applied to the control pins. in order to control the adg513, only 2.4 v are required for the on state and 0.8 v for the off state. if possible, use an input control signal whose amplitude ranges from 0.8 v to 2.4 v instead of a full range 0 v to 3.3 v/5 v for minimum pedestal error. other circuit features include an acquisition time of less than 3 m s to 1%; reducing c h and c2 will speed up the acquisition time further, but an increased pedestal error will result. settling time is less than 300 ns to 1%, and the sample-mode signal bw is 80 khz. the adg513 was chosen for its ability to work with 3 v/5 v supplies and for having normally-open and normally-closed pre- cision cmos switches on a dielectrically isolated process. sw2 is not required in this circuit; however, it was used in parallel with sw3 to provide a lower r on analog switch.
ad824 rev. a C15C fsy1 99 0 vp 1 fsy2 0 50 vn 1 dc1 25 99 dx dc2 50 25 dx * * models used * .model jx njf(beta=3.2526e-3 vto=-2.000 is=2e-12) .model npn npn(bf=120 vaf=150 var=15 rb=2e3 + re=4 rc=550 is=1e-16) .model pnp pnp(bf=120 vaf=150 var=15 rb=2e3 + re=4 rc=750 is=1e-16) .model dx d(is=1e-15) .model dy d() .model dq d(is=1e-16) .ends ad824 * ad824 spice macro-model 9/94, rev. a * arg/adi * * copyright 1994 by analog devices, inc. * * refer to readme.doc file for license statement. use of this model indicates your acceptance with the terms and provisions in the license statement. * * node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .subckt ad824 1 2 99 50 25 * * input stage & pole at 3.1 mhz * r3 5 99 1.193e3 r4 6 99 1.193e3 cin 1 2 4e-12 c2 5 6 19.229e-12 i1 4 50 108e-6 ios 1 2 1e-12 eos 7 1 poly(1) (12,98) 100e-6 1 j1425 jx j2476 jx * * gain stage & dominant pole * eref 98 0 (30,0) 1 r5 9 98 2.205e6 c3 9 25 54e-12 g1 98 9 (6,5) 0.838e-3 v1 8 98 -1 v2 98 10 -1 d1 9 10 dx d289dx * * common-mode gain network with zero at 1 khz * r21 11 12 1e6 r22 12 98 100 c14 11 12 159e-12 e13 11 98 poly(2) (2,98) (1,98) 0 0.5 0.5 * * pole at 10 mhz * r23 18 98 1e6 c15 18 98 15.9e-15 g15 98 18 (9,98) 1e-6 * * output stage * es 26 98 (18,98) 1 rs 26 22 500 ib1 98 21 2.404e-3 ib2 23 98 2.404e-3 d10 21 98 dy d11 98 23 dy c16 20 25 2e-12 c17 24 25 2e-12 dq1 97 20 dq q2 20 21 22 npn q3 24 23 22 pnp dq2 24 51 dq q5 25 20 97 pnp 20 q6 25 24 51 npn 20 vp 96 97 0 vn 51 52 0 ep 96 0 (99,0) 1 en 52 0 (50,0) 1 r25 30 99 5e6 r26 30 50 5e6
ad824 C16C rev. a outline dimensions dimensions shown in inches and (mm). 14-pin plastic (n) package (n-14) 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.795 (20.19) 0.725 (18.42) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) bsc pin 1 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) seating plane 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 7 8 14 1 14-pin soic (r) package (r-14) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 1 14 8 7 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) 0.3444 (8.75) 0.3367 (8.55) 0.0098 (0.25) 0.0040 (0.10) 16-pin soic package (r-16) 16 9 8 1 0.4133 (10.50) 0.3977 (10.00) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 printed in u.s.a. c1988aC2C1/97

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